1. Field of the Invention
Embodiments of the invention generally relate to methods for depositing materials on substrates, and more specifically, to methods for depositing dielectric materials utilized for fabricating a gate structure on substrates.
2. Description of the Related Art
Integrated circuits may include more than one million micro-electronic field effect transistors (e.g., complementary metal-oxide-semiconductor (CMOS) field effect transistors) that are formed on a substrate (e.g., semiconductor wafer) and cooperate to perform various functions within the circuit. A CMOS transistor comprises a gate structure disposed between source and drain regions that are formed in the substrate. The gate structure generally comprises a gate electrode and a gate dielectric layer. The gate electrode is disposed over the gate dielectric layer to control a flow of charge carriers in a channel region formed between the drain and source regions beneath the gate dielectric layer.
The gate dielectric layer has a thickness selected about 30 angstroms to 40 angstroms (Å), or less to achieve the desired speed of the transistor. However, conventional thermal silicon oxide (SiO2) dielectrics with thicknesses below 30 Å often have undesirable quality and decreased durability. For example, it is difficult to control the uniformity of SiO2 dielectric layers having a thickness less than 30 Å. Additionally, conventional deposited SiO2 dielectric layers generally have an undesirable amount of gate leakage current, i.e., tunneling current, which results in an increased amount of power consumed by the gate dielectric layer.
High-k dielectric materials (e.g., materials having a dielectric constant greater than 4) deposited by atomic layer deposition (ALD) have been widely applied in the gate structure application to obtain a low equivalent oxide thickness (EOT), and reduced gate leakage. Examples of high-k dielectric materials include silicon nitride, hafnium oxide, hafnium silicate, zirconium oxide and tantalum oxide and the like. During an ALD process, reactant gases are sequentially introduced into a process chamber containing a substrate. Generally, a first reactant is pulsed into the process chamber and is adsorbed onto the substrate surface. A second reactant is pulsed into the process chamber and reacts with the first reactant to form a substantially mono-atomic layer of deposited material. A purge step is typically carried out between the delivery of each reactant gas.
Typically, the surface topography of a substrate utilized for an ALD deposition process may determine the adsorbability of reactant gases provided by the ALD process. Poor adsorbability of reactant gases on the substrate surface may result in poor adhesion of the interfacial layer and subsequently deposited film. As gate structures become smaller and/or thinner to increase device speed, the quality and uniformity of the interfacial layer become increasingly important. Poor interfacial quality and non-uniformity of the deposited film will adversely impact the integration of the gate structure, resulting in high current leakage and low charge carrier mobility in the gate structures, which ultimately results in poor device performance.
Therefore, there is a need for an improved method for fabricating gate dielectric layers suitable for use in gate structures for field effect transistors.